A Novel Multi-Capture Scan Testing

System-on-a-chip is getting more and more popular in consumer and communication domains. The manufacturing test of SoC needs smart and economic test strategies. A novel scan testing method based on multi-capture scan testing (MCST) is proposed in this paper. Test vectors in MCST are utilized multiple times instead of once in traditional scan testing. MCST might reach the same fault coverage with fewer test vectors. To compress MCST test vectors, scan chain organization is optimized and its test generation method is presented. Multiple input signature register is used to compress test responses. Little aliasing and tiny fault coverage drop due to responses compression are proved by Galois field theory. Finally, experiments with ISCAS´89 benchmarks demonstrate that high compression ratio is achieved in MCST at the expense of only small fault coverage drop.