Title :
A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m
Author :
Lee, Hyung-Rok ; Kim, Ook ; Jung, Keewook ; Shin, John ; Jeong, Deog-Kyoon
Author_Institution :
Seoul Nat. Univ.
Abstract :
A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter components. The operating range using a narrow-range VCO is from 10 to 200MHz. The output jitter over this range is <0.028UIpp. The chip is implemented in a 0.18mum CMOS process and consumes 50mW from a 1.8V supply
Keywords :
1/f noise; CMOS integrated circuits; integrated circuit noise; jitter; phase locked loops; voltage-controlled oscillators; 0.18 micron; 1.8 V; 10 to 200 MHz; 50 mW; CMOS process; PVT-tolerant low-1/f noise; dual-loop hybrid PLL; jitter; large-bandwidth analog loop; phase locked loop; small-bandwidth digital loop; voltage controlled oscillator; 1f noise; Bandwidth; CMOS process; Clocks; Digital control; Digital filters; Frequency; Jitter; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696304
