Title :
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning
Author :
Brownlee, Merrick ; Hanumolu, Pavan Kumar ; Mayaram, Kartikeya ; Moon, Un-Ku
Author_Institution :
Oregon State Univ., Corvallis, OR
Abstract :
A PLL uses a fully differential supply-regulated tuning scheme to combat power-supply noise. The charge pump uses a resistor to set the current and reduce the flicker noise corner. Fabricated in a 0.18mum CMOS process, the PLL area is 0.15mm2. Operating at 2.4GHz, it has 3.29psrms jitter, a frequency range of 0.5 to 2.5GHz, and draws 14mA from a 1.8V supply
Keywords :
CMOS integrated circuits; UHF integrated circuits; circuit tuning; flicker noise; phase locked loops; voltage multipliers; 0.18 micron; 0.5 to 2.5 GHz; 1.8 V; 14 mA; CMOS process; charge pump; flicker noise corner; fully differential supply-regulated tuning; phase locked loop; power-supply noise; 1f noise; Charge pumps; Circuit noise; Delay; Low-frequency noise; Phase locked loops; Phase noise; Power supplies; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696305
