DocumentCode :
2571361
Title :
A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS
Author :
Von Büren, George ; Kromer, Christian ; Ellinger, Frank ; Huber, Alex ; Schmatz, Martin ; Jäckel, Heinz
Author_Institution :
ETH, Zurich
fYear :
2006
fDate :
6-9 Feb. 2006
Firstpage :
2462
Lastpage :
2471
Abstract :
A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes "0.5Vpp. The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply
Keywords :
CMOS integrated circuits; frequency dividers; millimetre wave integrated circuits; phase locked loops; 1 mA; 1.1 V; 2 mA; 31 to 41 GHz; 80 nm; CMOS integrated circuit; divide-by-4 circuit; dynamic frequency divider; phase locked loops; static frequency divider; Band pass filters; Bandwidth; Circuits; Design for disassembly; Energy consumption; Frequency conversion; Latches; Output feedback; Phase locked loops; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0079-1
Type :
conf
DOI :
10.1109/ISSCC.2006.1696310
Filename :
1696310
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2571361
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