DocumentCode :
2571365
Title :
A novel low power bus coding technique for nanometer technology
Author :
Zhao, Xin ; Tian, Xi ; Yan, ShaoShi ; Guan, Yongfeng
Author_Institution :
Nat. Univ. of Defense Technol., Changsha
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
1066
Lastpage :
1069
Abstract :
The power dissipation on data bus is becoming a significant contributor to total power dissipation of nanometer CMOS circuits. As technology scales, the inter-wire capacitance increases greatly. The power consumed on inter-wire capacitance exceeds on the grounded capacitance. In this paper, a new low power data bus coding technology is introduced which considers the inter-wire capacitance sufficiently. This method can be achieved with less hardware and the power dissipation can be reduced by 32.1% for 32-bit bus.
Keywords :
CMOS integrated circuits; capacitance; interwire capacitance; low power bus coding technique; nanometer CMOS circuits; nanometer technology; power dissipation; CMOS technology; Capacitance; Circuits; Data engineering; Equations; Hardware; Nanoscale devices; Paper technology; Power dissipation; Power engineering and energy; bus coding; inter-wire capacitance; low power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415817
Filename :
4415817
Link To Document :
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