DocumentCode
2571373
Title
A fixed-outline floorplanning method
Author
Yosihmura, Takeshi ; Chen, Song
Author_Institution
IPS Waseda Univ. Kitakyushu, Kitakyushu
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
1070
Lastpage
1075
Abstract
In this paper, we propose a stable fixed-outline floorplanning method (IARFP). An elaborated method for perturbing solutions, Insertion after Remove (IAR), is devised for the simulated annealing. The IAR operation uses the technique of enumerating positions in Sequence Pair and greatly accelerates the searching. Moreover, based on the analysis of diverse objective functions used in the existing researches, we suggest a new objective function, which is still effective when combined with other objectives, for the fixed-outline floorplanning. Compared with the previous fixed-outline floorplanners, the proposed method is effective and efficient. Experiments showed that the proposed fixed-outline floorplanner achieved 100% success rate efficiently when optimizing area and wire-length simultaneously, while getting much smaller wire-length. On the other hand, we validated once more by experiments that aspect ratio close to one is beneficial to wire-length.
Keywords
integrated circuit layout; simulated annealing; IARFP; IC technology; diverse objective function; fixed-outline floorplanning method; insertion after remove; integrated circuits; simulated annealing; Acceleration; Constraint optimization; Cost function; Perturbation methods; Production; Robustness; Simulated annealing; Transistors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415818
Filename
4415818
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