Title :
Floorplanning with constraint extraction based on interconnecting information analysis
Author :
Liu, Jiayi ; Dong, Sheqin ; Hong, Xianlong ; Goto, Satoshi
Author_Institution :
DCST of Tsinghua Univ., Beijing
Abstract :
After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.
Keywords :
VLSI; failure analysis; graph theory; integrated circuit layout; VLSI design; circuit design failure; floorplanning; geometric constraints extraction; graph theory; interconnecting information analysis; Data mining; Delay; Electronic design automation and methodology; High level synthesis; Information analysis; Integrated circuit interconnections; Joining processes; Strontium; Timing; Very large scale integration;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415821
