Title :
Performance maximized interlayer via planning for 3D ICs
Author :
Lu, Jun ; Chen, Song ; Yoshimura, Takeshi
Author_Institution :
Waseda Univ., Kitakyushu
Abstract :
As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit manufacture; 3D IC fabrication technology; integrated circuit interconnections; post-floorplanning stage; semiconductor industry; Delay estimation; Electronics industry; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Pins; Routing; Technology planning; Three-dimensional integrated circuits; White spaces;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415824
