DocumentCode :
2571511
Title :
Yield impact from physical design at advanced technology nodes
Author :
Kuei, Johnny ; Weng, Yulei
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
1104
Lastpage :
1109
Abstract :
As technology approach physical and atomic limit, designers need to understand yield impact with various physical design trade-offs. In this paper, we present various yield models and their relationship to physical layout in technology node 65 nm and beyond. We like to address (1) random, (2) systematic and (3) parametric variability yield models and how can physical design guidelines to reduce or minimize yield loss in those areas. One approach is to use restricted design rule, which tries to patch the technology marginality. One extreme case of reduced design rule is PdBrix which is use regular layout brick as design blocks. With limited blocks (less than 50), we can optimum designed blocks with respect to selected yield models as alternative to restricted DR approach or standard cell library.
Keywords :
integrated circuit layout; integrated circuit yield; CMOS scaling yield impact; PdBrix design rule; advanced technology nodes; physical design trade-offs; regular layout brick; size 65 nm; Electric breakdown; Fluctuations; Guidelines; Inspection; Libraries; Manufacturing processes; Power system modeling; Semiconductor device modeling; Stress; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415826
Filename :
4415826
Link To Document :
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