Title :
How to process a multi million gate ASIC layout in 21 hours
Author :
Ren, Haoxing ; Bercaw, Kevin ; Chadwick, Tom ; Guzowski, Tom ; Koehl, Juergen ; Miller, Jeff ; Urish, Steven
Abstract :
This paper discusses the turn around time reduction issue for the ASIC layout design process. It reviews key technologies to reduce the runtime of several of the most time consuming design steps. It also introduces a flexible yet easy to use reference layout design flow called FastTAT that is implemented in TheGuide, an IBM ASIC design methodology tool. The layout of a 17 million gate design has been processed within 21 hours from unplaced netlist to a fully routed and timing optimized design. Practical design issues related to turn around time are also discussed.
Keywords :
application specific integrated circuits; integrated circuit layout; network routing; FastTAT; fully routed design; multi million gate ASIC layout; reference layout design flow; turn around time reduction issue; Application specific integrated circuits; Clocks; Design methodology; Design optimization; Feedback; Logic design; Process design; Runtime; Time to market; Timing;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415829
