Abstract :
The paper describes two error detection and correction (EDAC) circuits designed and manufactured for the European space program. One of the EDACs is for a 16 bit data bus and the other for a 32 bit data bus. Eight check bits are added to the 16/32 data bits, giving the possibility to correct all single errors (SEC), detect all double errors (DED) and detect any memory chip failure (SBD), with a 4 or 8 bit per chip organization. Generally, SEC-DED-SBD require more check bits than the number of bits per chip. However, assuming all chip errors (but not the bit errors) to be permanent, the implemented (40,32) and (24,16) codes can be used to obtain SEC-DED-SBD for a 8 bit per chip organization. For a memory having 4 bits per chip, the codes are true SEC-DED-SBD. The codes are constructed by. Adding extra check bits to a reorganization of ordinary odd weight column SEC-DED codes. The extra check bits are considered not to require any extra memory, since the number of memory chips needed are the same for 22 as for 24 (39 as for 40) bits, when the organization is by 4 or by 8
Keywords :
aerospace computing; error correction codes; error detection codes; fault tolerant computing; microprocessor chips; reliability; space research; 16 bit data bus; 32 bit data bus; EDAC circuits; SEC-DED-SBD; check bits; chip errors; double error detection; error correcting circuits; error detecting circuits; error detection and correction; memory chip failure; memory chips; ordinary odd weight column SEC-DED codes; single error correction; space applications; Circuits; Computer errors; Embedded computing; Energy consumption; Error correction; Error correction codes; Packaging; Power system modeling; Protection; Pulp manufacturing;
