Verification techniques imposed upon design of a standard cell based dsp dedicated to cochlear implant

Digital circuit design is being challenged by ever-increasing design complexity and continuously shrinking transistor size. For high yield, we have to devote more to the design process, and the verifications carried during the design are becoming increasingly important. This paper takes a standard cell based DSP (digital signal processor) design as a case study to show the verification techniques adopted during the design process. This DSP is dedicated to a cochlear implant system. These methodologies form the architecture of multilevel verification. This multilevel verification architecture is not only well suited in our design, but can also be taken as a guideline to general ASIC (application specified integrated circuit) design process.