Title :
Design of 128QAM channel equalizer in FPGA
Author :
Du, Bin ; He, Zhiming
Author_Institution :
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
In All-digital IF receiver, the timing synchronization signal, due to inter-symbol interference will produce a high error rate, and then through the equalizer, eliminate inter-symbol interference. This paper uses CMA (constant modulus algorithm) to eliminate inter-symbol interference, and uses pipeline structure and complex multiplication optimization to improve processing speed, and save resources of FPGA.
Keywords :
equalisers; field programmable gate arrays; quadrature amplitude modulation; synchronisation; 128QAM channel equalizer design; CMA; FPGA; all-digital IF receiver; complex multiplication optimization; constant modulus algorithm; equalizer; inter-symbol interference; Adaptive equalizers; Blind equalizers; Convergence; Field programmable gate arrays; Optimization; Signal processing algorithms; Adaptive Equalizer; CMA; FPGA; Pipeline Structure;
Conference_Titel :
Computational Problem-Solving (ICCP), 2012 International Conference on
Conference_Location :
Leshan
Print_ISBN :
978-1-4673-1696-5
Electronic_ISBN :
978-1-4673-1695-8
DOI :
10.1109/ICCPS.2012.6384281
