Title :
VLSI power wiring noise analysis using MOR method
Author :
Saeki, Kosuke ; Miwa, Hitoshi ; Suzuki, Goro
Author_Institution :
Univ. of Kitakyushu, Kitakyushu
Abstract :
Demand for techniques to reduce verification time has been increasing in recent VLSI designs using sub-micron processes. The model order reduction (MOR) method by M.Celik et al. (2002) shortens verification time by reducing transfer functions order of the circuits. Employing the MOR method, we have developed a technique to analyze large scale power supply wirings of a whole DSP LSI chip. We have confirmed that our technique greatly improves circuit analysis capability maintaining sufficient accuracy.
Keywords :
VLSI; integrated circuit modelling; integrated circuit noise; power supply circuits; reduced order systems; wiring; DSP LSI chip; VLSI power wiring noise analysis; large scale power supply wiring; model order reduction method; Circuit analysis; Circuit noise; Digital signal processing chips; Large scale integration; Large-scale systems; Power supplies; Process design; Transfer functions; Very large scale integration; Wiring;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415846
