Title :
A fast-simulation model for post-layout SRAM
Author :
Jing, Xiaocheng ; Yao, Ruohe
Author_Institution :
South China Univ. of Technol., Guangzhou
Abstract :
A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.
Keywords :
random-access storage; microprocessor chips; post-layout SRAM; post-layout static random access memory; transistor-level simulation; Circuit simulation; Clocks; Decoding; Parameter extraction; Physics; Random access memory; SRAM chips; Signal generators; Timing; Transistors; SRAM; XRC; fast-simulation Model; layout; transistor-level simulation;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415849
