A method for electrical yield improvement for high speed polysilicon CMOS processed wafers

Author

Cernica, Ileana ; Manea, Elena ; Popescu, Alina M.

Author_Institution

Nat. Inst. for Res. & Dev. in Microtechnologies, Bucharest, Romania

Volume

2

fYear

2002

fDate

2002

Firstpage

339

Abstract

This paper presents the results obtained in optimization of metal deposition and sintering processes in order to raise the electrical yield of wafers in high speed polysilicon technology. We focused on the influence of the argon plasma presputter cleaning in situ process (parameter power and time), and sintering, and PSG deposition processes on values and dispersion of n⁺ contact resistance. Finally, we established some changes in the time and power for the argon plasma presputter cleaning sequence and also for the temperature, time and pull of sequence for the sintering process.

Keywords

CMOS integrated circuits; contact resistance; elemental semiconductors; integrated circuit metallisation; integrated circuit testing; integrated circuit yield; ohmic contacts; optimisation; plasma materials processing; silicon; sintering; sputter deposition; surface cleaning; Ar; CMOS wafer processing electrical yield improvement; P2O5-SiO2; PSG; PSG deposition; Si; cleaning power/time; contact resistance values/dispersion; in situ argon plasma presputter cleaning sequence; metal deposition optimization; ohmic contacts; polysilicon CMOS processed wafers; sintering process temperature/time/pull; Argon; CMOS process; CMOS technology; Circuit testing; Cleaning; Contact resistance; Current measurement; Measurement standards; Plasma measurements; Plasma temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2002. CAS 2002 Proceedings. International

Print_ISBN

0-7803-7440-1

Type

conf

DOI

10.1109/SMICND.2002.1105863

Filename

1105863