Simulation and performance analysis of network on chip architectures using OPNET

Network on chip (NoC) has been proposed as a solution for the problem of global interconnection in complex system on chip (SoC) design. To further enhance performance, the design parameters of the NoC should be chosen based on the application. In this paper, we use network simulator OPNET for modeling and simulating NoC at high level chip design. We investigate various configurations of NoC architectures by varying the network topologies (2D Mesh, Fat-Tree and Butterfly Fat-Tree) and switching techniques (wormhole and virtual-cut-through) and simulate each of these under different injection rates. Detailed comparative analysis of the simulation results in terms of latency and throughput are presented. Results show that FT topology with WH switching technique for NoC architecture design can achieve optimal performance.