DocumentCode :
2572385
Title :
Stress analysis of shallow trench isolation for 256 M DRAM and beyond
Author :
Kuroi, Takashi ; Uchida, Tomoyuki ; Horita, K. ; Sakai, Masayuki ; Inoue, Yasuyuki ; Nishimura, T.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
fYear :
1998
fDate :
6-9 Dec. 1998
Firstpage :
141
Lastpage :
144
Abstract :
The stress generation of the shallow trench isolation has been systematically investigated using the stress simulation and the experiment. It is found that the scale-down of the isolation pitch causes a remarkable stress generation due to the overlap of the stress from both trench sides. Therefore a small isolation pitch causes the crystal defects generation with ease. We carried out the stress analysis against the various process parameters in detail. The high temperature sacrificial oxidation can effectively eliminate the stress generation. It was confirmed that enough isolation characteristics can maintain up to 0.1 /spl mu/m regime to give a careful consideration of the stress reduction.
Keywords :
CMOS memory circuits; DRAM chips; ULSI; crystal defects; isolation technology; oxidation; stress analysis; 0.1 micron; 256 Mbit; DRAM; crystal defects generation; high temperature sacrificial oxidation; isolation pitch; process parameters; scale-down; shallow trench isolation; stress analysis; stress generation; Elasticity; Electronic mail; Etching; Lapping; Oxidation; Stress; Temperature; Ultra large scale integration; Viscosity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4774-9
Type :
conf
DOI :
10.1109/IEDM.1998.746300
Filename :
746300
Link To Document :
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