Title :
Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)
Abstract :
The following topics are dealt with: ASIC; SOPC; dynamic instruction scheduling; VLIW-DISVLIW; SoC integration; programmable cores; logic development; software-defined radio; NoC; CMOS; electronic ballasts; fluorescent lamps; application mapping; network simulation; network-on-chip; code compression scheme; AMBA; multiprocessor system; CTL; matrix inverse; fixed-point representation; iterative methods; network processor; low power datapath; algebraic codebook search; system-on-chip; complexity analysis; MPEG-4 encoder; application specific algorithms; IP-methodology; compressed transport; C-based algorithm; reconfigurable processor architecture; XICU; interrupt control unit; DSP; interconnects; inductive crosstalk; capacitive crosstalk; noise cancellation; dynamic clamping; dynamic shielding; RLC buses; communication generator; arithmetic processing unit; reciprocal operations; routing algorithm; mappability estimate; processor-algorithm pair; multiple-objective backtrace; test generation constraints; IP integration; energy consumption; delay spread; FFT processor; wireless receivers; Ethernet; loopback BIST; RF front-ends; digital transceivers; RTOS modelling; multiprocessors; flip-flops; integrated circuits; switching regulators; static profiling; dynamic profiling; code compression; AVISPA; and reconfigurable accelerator.
Keywords :
CMOS integrated circuits; application specific integrated circuits; digital signal processing chips; integrated circuit design; iterative methods; logic design; logic programming; multiprocessing programs; multiprocessing systems; processor scheduling; reconfigurable architectures; system-on-chip; transceivers; AMBA; ASIC; AVISPA; C-based algorithm; CMOS; CTL; DSP; Ethernet; FFT processor; IP integration; IP-methodology; MPEG-4 encoder; NoC; RF front-ends; RLC buses; RTOS modelling; SOPC; SoC integration; VLIW-DISVLIW; XICU; algebraic codebook search; application mapping; application specific algorithms; arithmetic processing unit; capacitive crosstalk; code compression scheme; communication generator; complexity analysis; compressed transport; delay spread; digital transceivers; dynamic clamping; dynamic instruction scheduling; dynamic profiling; dynamic shielding; electronic ballasts; energy consumption; fixed-point representation; flip-flops; fluorescent lamps; inductive crosstalk; integrated circuits; interconnects; interrupt control unit; iterative methods; logic development; loopback BIST; low power datapath; mappability estimate; matrix inverse; multiple-objective backtrace; multiprocessor system; multiprocessors; network processor; network simulation; network-on-chip; noise cancellation; processor-algorithm pair; programmable cores; reciprocal operations; reconfigurable accelerator; reconfigurable processor architecture; routing algorithm; software-defined radio; static profiling; switching regulators; system-on-chip; test generation constraints; wireless receivers; Application specific integrated circuits; CMOS integrated circuits; Digital signal processors; Integrated circuit design; Iterative methods; Logic design; Logic programming; Multiprocessing; Processor scheduling; Reconfigurable architectures; Transceivers;
Conference_Titel :
System-on-Chip, 2003. Proceedings. International Symposium on
Conference_Location :
Tampere
Print_ISBN :
0-7803-8160-2
DOI :
10.1109/ISSOC.2003.1267700
