SoC integration of programmable cores

SystemC is considered as the emerging industry standard for system architecture design, because on the one hand side being a native C++ library it fits well into any SW flow. On the other hand side, SystemC incorporates mandatory HW semantics like concurrency, module hierarchy, and explicit timing to create architectural models. However, having an expressive language alone is not sufficient to enable system-level design, instead the major bottleneck in terms of simulation speed and modelling efficiency is caused by the highly detailed register-transfer level (RTL) modelling style. Therefore, SystemC 2.0 advocates the transaction-level modelling (TLM) paradigm, where the pin-accurate communication between modules is replaced by condensed interface method calls. Especially for complex bus protocols like AMBA AHB, this simplification attains up to two orders in simulation efficiency without sacrificing cycle accuracy. TLM along with the concept of dynamic sensitivity also results in a very condensed modelling style, which is essential to motivate the creation and maintenance of a separate model for architectural exploration at the system level.