A new ESD-aware power amplifier design method

Author

Guan, Xiaokang ; Chen, Guang ; Lin, Lin ; Xin Wang ; Wang, Xin ; Yang, Lee ; Zhao, Bin

Author_Institution

California Univ., Riverside

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

1363

Lastpage

1366

Abstract

This paper presents a new ESD-aware power amplifier (PA) design method, featuring S-parameter modeling and output impedance re-matching techniques, to achieve ESD+PA full-chip design optimization. The new method is verified using a 5 kV ESD-protected 2.4 GHz PA circuit designed and implemented in a 0.18 mum RFCMOS technology. Experiment shows substantial performance degradation of PA due to ESD effect, which can be recovered by using the new ESD-aware ESD design method.

Keywords

CMOS integrated circuits; S-parameters; UHF integrated circuits; UHF power amplifiers; electrostatic discharge; impedance matching; integrated circuit design; ESD-aware power amplifier design method; PA circuit designed; RF CMOS technology; S-parameter modeling; frequency 2.4 GHz; full-chip design optimization; output impedance re-matching techniques; size 0.18 micron; Design methodology; Design optimization; Diodes; Electrostatic discharge; Impedance matching; Integrated circuit noise; Power amplifiers; Protection; Radio frequency; Radiofrequency integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415890

Filename

4415890