A high performance 180 nm generation logic technology

Author

Yang, S. ; Ahmed, S. ; Arcot, B. ; Arghavani, R. ; Bai, P. ; Chambers, S. ; Charvat, P. ; Cotner, R. ; Gasser, R. ; Ghani, T. ; Hussein, M. ; Jan, C. ; Kardas, C. ; Maiz, J. ; McGregor, P. ; Mcintyre, B. ; Nguyen, P. ; Packan, P. ; Post, I. ; Sivakumar, S

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

197

Lastpage

200

Abstract

A 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low-/spl epsi/ SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO/sub 2/ inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 /spl mu/m/sup 2/ 6-T cell size have been built on this technology as a yield and reliability test vehicle.

Keywords

SRAM chips; integrated circuit interconnections; integrated logic circuits; low-power electronics; 1.3 to 1.5 V; 16 Mbit; 180 nm; Al; SRAM; SiOF; SiOF dielectric; aluminum interconnect; capacitance; logic technology; metal line; reliability; resistance; transistor; yield; Aluminum; Boron; Capacitance; Dielectrics; Implants; Integrated circuit interconnections; Logic; Microprocessors; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746320

Filename

746320