Title :
A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operation
Author :
Ishida, M. ; Kawakami, T. ; Tsuji, A. ; Kawamoto, N. ; Motoyoshi, M. ; Ouchi, N.
Author_Institution :
Syst. LSI Div., Sony Corp., Atsugi, Japan
Abstract :
A novel 6T-SRAM cell layout designed with rectangular patterns has been developed. Employing this layout, 4.13 /spl mu/m/sup 2/ and 5.33 /spl mu/m/sup 2/ cells with word transistor width of 0.25 /spl mu/m and 0.75 /spl mu/m are obtained, respectively, based on the 0.20 /spl mu/m rule. Among the various layouts of 6T-SRAM cells, this layout provides minimum cell size and the smallest bit line capacitance with word transistor width over 0.75 /spl mu/m for the ultra high speed operation. It is also demonstrated quantitatively that the optimized SRAM cell layout for high speed use is different from that for low power use. The cell layout proposed also provides the excellent scalability beyond 0.18 /spl mu/m generation due to its highly simplified pattern design.
Keywords :
SRAM chips; high-speed integrated circuits; integrated circuit layout; integrated circuit technology; 0.18 micron; 6T-SRAM cell technology; bit line capacitance; design; layout; rectangular pattern; scalability; ultra high speed operation; word transistor size; Capacitance; Central Processing Unit; Circuits; Decoding; Delay; Large scale integration; Lithography; Random access memory; Scalability; Wiring;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746322
