A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

A 0.2-/spl mu/m bipolar-CMOS process technology on a bonded SOI wafer was developed for ultra-high-speed applications. This process was used to fabricate a new cache memory chip consisting of 9-Mb 0.6-ns SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-/spl mu/m bipolar-CMOS process features a 6-/spl mu/m/sup 2/-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SOI wafer with deep and shallow trench isolations was used to maximize the BJT performance.