A code compression scheme for improving SoC performance

Code compression is an effective technique for reducing the instruction memory requirement in an embedded system. This paper presents a code compression approach in which the boundary between compressed and uncompressed space lays between the instruction cache (ICache) and the microprocessor core. The approach achieves better compression ratios (around 0.57) than other reported implementations, and, as the ICache holds compressed instructions, its effective size is increased and the hit ratio is improved. The implementation of branch prediction as part of the decompression hardware further improves the system´s performance. The work has required the resolutions of issues that arise from both memory and ICache data misalignment and form the compressed to uncompressed address mapping.