Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

Author

Hatirnaz, I. ; Leblebici, Y.

Author_Institution

Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

fYear

2003

fDate

19-21 Nov. 2003

Firstpage

93

Lastpage

96

Abstract

A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed 3-D simulations show that a crosstalk noise reduction of up to 60 dB is achievable with this approach.

Keywords

circuit simulation; integrated circuit interconnections; integrated circuit noise; 3-D simulations; capacitive noise; crosstalk noise cancellation; crosstalk noise reduction; generic interconnect architecture; inductive noise; mutual coupling; on-chip interconnect architecture; on-chip interconnect lines; parallel interconnect; twisted differential line pairs; Circuit noise; Coupling circuits; Crosstalk; Delay estimation; Integrated circuit interconnections; Microelectronics; Noise reduction; System-on-a-chip; Transmission lines; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2003. Proceedings. International Symposium on

Print_ISBN

0-7803-8160-2

Type

conf

DOI

10.1109/ISSOC.2003.1267725

Filename

1267725