A driver load model for capacitive coupled on-chip interconnect buses

An analytical model is derived for capacitive coupled on-chip interconnect buses. If an estimation of the wire length is available, the driver output can be estimated using the load model and take coupling effects on the interconnect tree into account. The load is modeled as π-network which depends on the first three moments of the exact admittance function of the bus system. Simulations with specterS have shown, that the model represents a good approximation for the driver load of a distributed interconnect bus tree. It is proven mathematically that the model remains passive.