Using a communication generator in SoC architecture exploration

This paper presents an implementation of a communication generator, named transaction generator. It is utilized in communication-centric SoC architecture exploration where the objective is to find the optimal hardware allocation, task partitioning, and scheduling with a given application model and architectural requirements. An application is abstracted with a process network model of computation and architecture is described with characteristic metrics. In addition to accelerating architecture exploration, transaction generator can be used in development, verification and comparison of on-chip communication networks.