Modeling of grain size variation effects in polycrystalline thin film transistors

A strategy is presented for modeling of performance variation in polycrystalline thin film transistors (TFTs) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFTs results in reasonable agreement.