Title :
A delay spread based low power reconfigurable FFT processor architecture for wireless receiver
Author :
Hasan, M. ; Arslan, T. ; Thompson, J.S.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ., UK
Abstract :
This paper proposes a novel concept of adjusting the FFT size in real time as per the delay spread in wireless receivers. The FFT size in OFDM/MC-CDMA based wireless receivers varies from 1024(1k)-point to 16-point. A low power reconfigurable radix-4 1k-point FFT processor architecture is proposed that can also be configured as a 256-point, 64-point or 16-point as per the channel parameters. By tailoring the clock of the higher FFT stages for longer FFT´s, significant power saving is achieved by switching to shorter FFTs from longer FFTs.
Keywords :
code division multiple access; fast Fourier transforms; low-power electronics; microprocessor chips; radio receivers; reconfigurable architectures; 16-point configuration; 1k-point FFT processor architecture; 256-point configuration; 64-point configuration; FFT size; MC-CDMA; OFDM; channel parameters; delay spread; low power FFT processor; low power reconfigurable radix-4; reconfigurable FFT processor architecture; wireless receiver; Bandwidth; Bit error rate; Clocks; Decoding; Delay effects; Flexible printed circuits; Multiaccess communication; Multicarrier code division multiple access; OFDM; Viterbi algorithm;
Conference_Titel :
System-on-Chip, 2003. Proceedings. International Symposium on
Print_ISBN :
0-7803-8160-2
DOI :
10.1109/ISSOC.2003.1267736
