Solder paste optimization in thermal pad padstack

In this paper is presented an important solder paste optimization for thermal pads used for Quad Flat No leads (QFNs) and Small Outline No leads (SONs) packages. The PCB (printed circuit board) must be designed to have an excellent heat conductivity for them, incorporating a thermal pad and thermal vias on it. This can be achieved by creating a special padstack for thermal pad, with a complex solder paste, created in a matrix of squares leaving channels for thermal vias. This way, the quantity of solder paste used in fabrication process is smaller than the case of a full filled solder paste pad, avoiding solder leakage through vias. The novelty of the paper is represented by creating a complex solder paste pad, using a template, like a starting point for the rest of thermal pads included in Mentor Graphics Expedition software library.