Title :
FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1M bit FRAM
Author :
Tanaka, S. ; Ogiwara, R. ; Itoh, Y. ; Miyakawa, T. ; Takeuchi, Y. ; Doumae, S. ; Takenaka, H. ; Kamata, H.
Author_Institution :
ULSI Device Eng. Lab., Toshiba Corp., Japan
Abstract :
A new FRAM cell design with high immunity to fatigue and imprint has been proposed to achieve a megabit class FRAM with 1T1C cell structure, which has been applied to a 1M bit FRAM operated from a 3 V supply with 1T1C cell structure, 0.5 /spl mu/m rule and 3 /spl mu/m/sup 2/ capacitor area. The simulation result and imprint data predict a lifetime improved 7 orders longer than the conventional scheme.
Keywords :
ferroelectric storage; low-power electronics; random-access storage; 0.5 micron; 1 Mbit; 1T1C FRAM cell design; 3 V; fatigue; ferroelectric random access memory; imprint; simulation; Capacitors; Fatigue; Ferroelectric films; Graphics; Hysteresis; Nonvolatile memory; Polarization; Pulse measurements; Random access memory; Voltage;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746374
