Capacitor-on-metal/via-stacked-plug (CMVP) memory cell for 0.25 /spl mu/m CMOS embedded FeRAM

Author

Amanuma, K. ; Tatsumi, T. ; Maejima, Y. ; Takahashi, S. ; Hada, H. ; Okizaki, H. ; Kunio, T.

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

363

Lastpage

366

Abstract

A capacitor-on-metal/via-stacked-plug (CMVP) memory cell was developed for 0.25 /spl mu/m CMOS logic embedded FeRAM. Using 445/spl deg/C MOCVD Pb(Zr,Ti)O/sub 3/ process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables cell size reduction (3.2 /spl mu/m/sup 2/ for 1T1C), minimum process damage on ferroelectric, and low manufacturing cost.

Keywords

CMOS digital integrated circuits; MOCVD; cellular arrays; ferroelectric capacitors; ferroelectric storage; lead compounds; memory architecture; random-access storage; titanium compounds; zirconium compounds; 0.25 micron; 445 degC; CMOS embedded FeRAM; CMOS logic fabrication; MOCVD; PZT; PbZrO3TiO3; capacitor-on-metal/via-stacked-plug; cell size reduction; ferroelectric capacitor; manufacturing cost; memory cell; process damage; CMOS logic circuits; CMOS process; Capacitors; Fabrication; Ferroelectric films; Ferroelectric materials; Logic devices; MOCVD; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746375

Filename

746375