Ultra thin (<20 /spl Aring/) CVD Si/sub 3/N/sub 4/ gate dielectric for deep-sub-micron CMOS devices

Author

Song, S.C. ; Luan, H.F. ; Chen, Y.Y. ; Gardner, M. ; Fulford, J. ; Allen, M. ; Kwong, D.L.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

373

Lastpage

376

Abstract

In this paper, we report the first sub-micron n- and p-MOSFETs with ultra thin (<20 /spl Aring/) Si/sub 3/N/sub 4/ gate dielectric fabricated by in-situ rapid thermal CVD (RTCVD) process, and compare their performance and reliability with control SiO/sub 2/ devices of identical equivalent oxide thickness (T/sub eq/). Both n- and p-MOSFETs with CVD Si/sub 3/N/sub 4/ gate dielectric show higher drain current and peak transconductance, enhanced immunity to hot carrier stress, and significant reduction of tunneling leakage current.

Keywords

CVD coatings; MOSFET; dielectric thin films; hot carriers; leakage currents; rapid thermal processing; semiconductor device reliability; 20 angstrom; CVD; Si/sub 3/N/sub 4/; deep-sub-micron CMOS devices; drain current; hot carrier stress; in-situ rapid thermal process; n-MOSFETs; p-MOSFETs; peak transconductance; reliability; tunneling leakage current; ultra thin gate dielectric; Dielectric devices; Electron traps; Hot carriers; Interface states; Leakage current; MOSFET circuits; Passivation; Thickness control; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746377

Filename

746377