DocumentCode :
2573360
Title :
High quality ultra-thin TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric for giga scale MOS technology
Author :
Xin Guo ; Ma, T.P. ; Tamagawa, T. ; Halpern, B.L.
Author_Institution :
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
fYear :
1998
fDate :
6-9 Dec. 1998
Firstpage :
377
Lastpage :
380
Abstract :
This paper presents the study of physical and electrical properties of ultra-thin (2.0-3.0 nm EOT) TiO/sub 2//Si/sub 3/N/sub 4/ stack gate dielectrics for future giga scale MOS technology. Both layers of the dielectric stack are deposited by the jet vapor deposition (JVD) process. Our experimental data indicate that the leakage current in the TiO/sub 2//Si/sub 3/N/sub 4/ stack is substantially (several decades) lower than that in single oxide layer of the same equivalent oxide thickness (EOT). These films also exhibit excellent interface quality, dielectric reliability, and MOSFET transistor performance comparable to that of thermal oxide.
Keywords :
CMOS integrated circuits; MIS capacitors; MOSFET; ULSI; dielectric thin films; diffusion barriers; integrated circuit reliability; leakage currents; permittivity; silicon compounds; titanium compounds; vapour deposited coatings; 2.0 to 3.0 nm; MOSFET transistor performance; TiO/sub 2/-Si/sub 3/N/sub 4/-Si; dielectric reliability; equivalent oxide thickness; giga scale MOS technology; interface quality; jet vapor deposition; leakage current; stack gate dielectrics; ultra-thin gate dielectric; Annealing; Atomic layer deposition; Dielectric substrates; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Nitrogen; Optical films; Titanium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4774-9
Type :
conf
DOI :
10.1109/IEDM.1998.746378
Filename :
746378
Link To Document :
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