DocumentCode
2573422
Title
An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer
Author
Wakabayashi, H. ; Yamamoto, T. ; Yoshida, K. ; Soda, E. ; Tokunaga, K. ; Mogami, T. ; Kunio, T.
Author_Institution
Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan
fYear
1998
fDate
6-9 Dec. 1998
Firstpage
393
Lastpage
396
Abstract
Advanced tungsten/pn-poly-Si gate CMOS devices with ultra-low resistance of 1 /spl Omega///spl square/ have been demonstrated using Si/TiN buffer layer. Propagation delay time of inverter ring oscillator with this novel gate CMOS is greatly smaller than that with Co-salicide CMOS in wider channel width.
Keywords
CMOS integrated circuits; integrated circuit metallisation; tungsten; CMOS technology; Si-TiN; Si/TiN buffer layer; W-Si; inverter ring oscillator; propagation delay time; resistance; thermal stability; tungsten/pn-poly-Si gate; Buffer layers; CMOS logic circuits; CMOS technology; Conductivity; Electrodes; Grain size; Logic devices; Thermal resistance; Tin; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-4774-9
Type
conf
DOI
10.1109/IEDM.1998.746382
Filename
746382
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