Title :
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET´s at the 25 nm channel length generation
Author :
Wong, H.-S.P. ; Frank, D.J. ; Solomon, P.M.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET´s are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.
Keywords :
MOSFET; silicon-on-insulator; 25 nm; buried insulator; design; double-gate device; gate insulator; ground plane; short-channel effect; simulation; single-gate device; two-dimensional field effect; ultrathin SOI MOSFET; Analytical models; CMOS technology; Dielectrics and electrical insulation; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Silicon on insulator technology; Space exploration; Space technology; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746385
