Title :
Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications
Author :
Miyamoto, M. ; Nagai, R. ; Nagano, T.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A "pseudo-SOI (P-SOI)" MOSFET using a bulk substrate with small subthreshold swing, high drain current, low junction capacitance, and low substrate-bias coefficient comparable to those of thin-film SOI MOSFET has been developed. The P-SOI MOSFET features a P-N-P channel profile, in which the sandwiched N-type layer is fully depleted by the internal built-in potential. Fabricated 0.25-/spl mu/m P-SOI MOSFET achieves subthreshold swing of 73 mV/decade and had a 25% larger drain current, 60% lower source/drain junction capacitance, and 40% lower substrate-bias coefficient than those of a control MOSFET.
Keywords :
MOSFET; doping profiles; low-power electronics; silicon-on-insulator; 0.25 micron; P-N-P channel doping profile; drain current; junction capacitance; low-voltage device; pseudo-SOI MOSFET; substrate bias coefficient; subthreshold swing; Capacitance; Insulation; Low voltage; MOSFET circuits; Substrates; Subthreshold current; Thermal conductivity; Threshold voltage; Tin; Transistors;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746386