Title :
Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology
Author :
Kotaki, H. ; Kakimoto, S. ; Nakano, M. ; Adachi, K. ; Shibata, A. ; Sugimoto, K. ; Ohta, K. ; Hashizume, N.
Author_Institution :
Central Res. Labs., Sharp Corp., Nara, Japan
Abstract :
We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation. This was realized using sidewall elevated drain. The LCSED achieved the following excellent characteristics as compared to the bulk-DTMOS which we proposed earlier: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current. These effects realize ultra low power high speed operation.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; high-speed integrated circuits; leakage currents; low-power electronics; LCSED; dual gate CMOS technology; dynamic threshold voltage MOSFET; forward leakage current reduction; high speed MOSFET; junction capacitance reduction; low capacitance MOSFET; short channel effect; sidewall elevated drain; transistor series resistance reduction; ultra low power CMOS technology; Batteries; CMOS technology; Capacitance; Electrodes; Immune system; Leakage current; MOSFET circuits; Power MOSFET; Power supplies; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746387
