A new methodology for dynamic reconfiguration of structured ASIC

This paper presents the methodology and EDA software for dynamic reconfiguration of structured ASIC technology. New dynamic reconfigurable architectures introduced for structured ASIC offer a solution to use both temporal and spatial capacity of logic devices. The proposed solution reuses stages of standard implementation flow for structured ASIC and adds custom EDA software for programming and reconfiguration. The methodology is separated in two stages: pre-fabrication and post-fabrication. While the pre-fabrication stage uses the standard flow of implementing structured ASIC circuits the post fabrication programming is a new stage build around custom EDA software. This stage uses a behavioral Verilog description of the circuit to generate a memory image that can be loaded into the structured ASIC in order to change the circuit logic function. Device functionality can be modified at each power-up cycle by loading the memory image from external memory or during application execution to allow rapid dynamic logic reconfiguration.