Title :
Wire Segmenting For Improved Buffer Insertion
Author :
Alpert, Charles ; Devgan, Anirudh
Author_Institution :
IBM Austin Research Laboratory, Austin, TX 78758
Keywords :
Central Processing Unit; Delay; Heuristic algorithms; Integrated circuit interconnections; Laboratories; Libraries; Permission; Routing; Topology; Wire;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597214
