Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

To sustain the silicon CMOS scaling beyond 100 nm, an alternate gate dielectric with K>7 is needed. The deposited high K dielectrics (metal oxides) have nonstoichiometric composition and therefore have large electrical defects (traps) in the bulk of the dielectric and at the dielectric/semiconductor interface. In this paper, we report a novel doping method to quench traps in thin films of Al/sub 2/O/sub 3/ (K>8). By adding small amounts of dopants such as Zirconium (Zr) or Silicon (Si), we have achieved /spl sim/10nm thick aluminum oxide films with record low leakage current (<10/sup -13/A/mm/sup 2/) and ultra-thin (3-5 nm) aluminum oxide films with 2 very low interface state density (/spl sim/10/sup 10//cm/sup 2/-eV) at the silicon/aluminum oxide interface. We propose a physics based model for the doping effect and selection of dopants for metal oxides with K>10.