Ultra thin high quality Ta/sub 2/O/sub 5/ gate dielectric prepared by in-situ rapid thermal processing

Author

Luan, H.F. ; Wu, B.Z. ; Kang, L.G. ; Kim, B.Y. ; Vrtis, R. ; Roberts, D. ; Kwong, D.L.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

609

Lastpage

612

Abstract

In this paper, ultra thin CVD Ta/sub 2/O/sub 5/ gate dielectrics (Teq<15 /spl Aring/) with significantly lower leakage current compared to SiO/sub 2/, of identical thickness, have been fabricated by in-situ RTP processing. Superior interface properties and reliability have been obtained.

Keywords

CMOS integrated circuits; CVD coatings; MOS capacitors; MOS integrated circuits; MOSFET; chemical vapour deposition; dielectric thin films; failure analysis; integrated circuit reliability; integrated circuit technology; leakage currents; rapid thermal processing; tantalum compounds; 15 A; MOS capacitor; MOSFET technology; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ gate dielectric; high quality gate dielectric; in-situ RTP processing; interface properties; leakage current; rapid thermal processing; reliability; ultra thin films; Annealing; Capacitance-voltage characteristics; Dielectric materials; Leakage current; MOS capacitors; Material storage; Microelectronics; Passivation; Rapid thermal processing; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746432

Filename

746432