A 1.9-/spl mu/m/sup 2/ loadless CMOS four-transistor SRAM cell in a 0.18-/spl mu/m logic technology

Author

Noda, K. ; Matsui, K. ; Imai, K. ; Inoue, K. ; Tokashiki, K. ; Kawamoto, H. ; Yoshida, K. ; Takeda, K. ; Nakamura, N. ; Kimura, T. ; Toyoshima, H. ; Koishikawa, Y. ; Maruyama, S. ; Saitoh, T. ; Tanigawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

643

Lastpage

646

Abstract

We present a loadless CMOS four-transistor cell for very high-density embedded SRAM applications. Using 0.18-/spl mu/m CMOS technology, the memory cell size is 1.9344 /spl mu/m/sup 2/ (1.04 /spl mu/m/spl times/1.86 /spl mu/m), which is 35% smaller than a six-transistor cell using the same design rule. The newly developed CMOS 4T cell operates with high stability at 1.8 V, even though its designed cell ratio is 1.0 to minimize the area. A pair of pMOS transfer transistors is used to store and retain full-swing signals in the cell without a refresh cycle. The fabrication process is fully compatible with high performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load.

Keywords

CMOS memory circuits; SRAM chips; circuit stability; 0.18 micron; 1.8 V; CMOS four-transistor SRAM cell; CMOS logic technology; fabrication process; high stability; high-density embedded SRAM applications; loadless SRAM cell; pMOS transfer transistors; static RAM; CMOS logic circuits; CMOS technology; Equivalent circuits; Etching; Joining processes; Logic circuits; MOSFET circuits; Plugs; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746440

Filename

746440