A high-performance area-aware DSP processor architecture for video codecs

In this paper, we propose a high-performance and area-aware very long instruction word (VLIW) DSP architecture using a flexible single instruction multiple data (SIMD) approach and a grouped permutation (GP) structure register file, respectively. Via the proposed data path architecture, the reduction of the execution cycles for digital filter and RGB2YUV benchmarks can be improved up to 50% compared with that of Hinrichs et al. (2000) and Lin et al. (2003). For motion estimation, the number of pixels per cycle applying the proposed architecture can be four times than that of Hinrichs and Lin. For the register file, using the proposed GP structure, the saving of switching network overhead can be anticipated compared with the work in Lin