Synchronization for QDPSK —Costas loop and Gardner algorithm using FPGAs

Author

Jie Hua ; Lingyun Zhou ; Chang Chen ; Lin Jiang

Author_Institution

Key Lab. of Electromagn. Space Inf., Univ. of Sci. & Technol. of China, Hefei, China

fYear

2014

fDate

4-6 June 2014

Firstpage

27

Lastpage

31

Abstract

This paper discusses the mathematical model and implements the physical verification when Carrier synchronization (carrier loop) and Timing synchronization (Gardner algorithm) working simultaneously. Firstly, a brief analysis of the above mentioned systems is completed, and the functional simulation is accomplished by Verilog HDL code on ModelSim platform. In addition, a systematic analysis is done for the workflow and interrelation of Carrier synchronization and Timing synchronization when both of them are active. Finally, we implement the hardware verification on the Stratix series field programmable gate array (FPGA) device EP3SL150F1152C2N of Altera Company, and give the engineering results through the RF part and space transmission.

Keywords

differential phase shift keying; field programmable gate arrays; hardware description languages; quadrature phase shift keying; synchronisation; Altera Company; Costas loop; FPGA device EP3SL150F1152C2N; Gardner algorithm; ModelSim platform; QDPSK; Stratix series field programmable gate array; Verilog HDL code; carrier loop; carrier synchronization; functional simulation; hardware verification; mathematical model; physical verification; systematic analysis; timing synchronization; Algorithm design and analysis; Detectors; Field programmable gate arrays; Finite impulse response filters; Matched filters; Synchronization; Carrier synchronization; FPGA; Timing synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Information Science (ICIS), 2014 IEEE/ACIS 13th International Conference on

Conference_Location

Taiyuan

Type

conf

DOI

10.1109/ICIS.2014.6912102

Filename

6912102