Synchronization for QDPSK —Costas loop and Gardner algorithm using FPGAs

This paper discusses the mathematical model and implements the physical verification when Carrier synchronization (carrier loop) and Timing synchronization (Gardner algorithm) working simultaneously. Firstly, a brief analysis of the above mentioned systems is completed, and the functional simulation is accomplished by Verilog HDL code on ModelSim platform. In addition, a systematic analysis is done for the workflow and interrelation of Carrier synchronization and Timing synchronization when both of them are active. Finally, we implement the hardware verification on the Stratix series field programmable gate array (FPGA) device EP3SL150F1152C2N of Altera Company, and give the engineering results through the RF part and space transmission.