DocumentCode
2574573
Title
Lateral thinking about power devices (LDMOS)
Author
Efland, T.R. ; Chin-Yu Tsai ; Pendharkar, S.
Author_Institution
Power Device Dev., Texas Instrum. Inc., Dallas, TX, USA
fYear
1998
fDate
6-9 Dec. 1998
Firstpage
679
Lastpage
682
Abstract
BiCMOS Power technology LDMOS are reviewed with respect to category and structure definition and briefly as to how the structures relate to figure of merit performance. Stepped gate oxide devices are introduced making use of popular dual gate technologies and exhibit improved R/sub sp/ vs. BV performance of up to 30% at low V/sub gs/ without sacrifice of BV. Production use of thick copper plated bussing up to 25 /spl mu/m thick with R/sub sh/=0.8 m/spl Omega//sq is revealed for power, enabling up to 40% efficiency improvement on LDMOS power transistors.
Keywords
power MOSFET; BiCMOS power technology; Cu; LDMOS power transistor; copper plated bus; dual gate technology; figure of merit; stepped gate oxide device; BiCMOS integrated circuits; Contact resistance; Copper; Immune system; Instruments; Logic devices; Low voltage; Physics; Space technology; Surface resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-4774-9
Type
conf
DOI
10.1109/IEDM.1998.746447
Filename
746447
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