Title :
A versatile 0.25 micron CMOS technology
Author :
Poon, S. ; Atwell, C. ; Hart, C. ; Kolar, D. ; Lage, C. ; Yeargain, B.
Author_Institution :
Semicond. Products Sector, Motorola Inc., Austin, TX, USA
Abstract :
Manufacturing issues concerning 0.25 micron CMOS technologies including devices for high performance processor, dense SRAM, and low power circuits are discussed. Tradeoffs between performance, cost, and statistical effects such as gate length and Vt control are presented. Requirements for future technologies are identified to improve maturity prior to implementation.
Keywords :
CMOS integrated circuits; integrated circuit manufacture; 0.25 micron; dense SRAMs; gate length; high performance processors; low power circuits; manufacturing issues; statistical effects; submicron CMOS technology; threshold voltage control; CMOS technology; Cobalt; Costs; Implants; Integrated circuit interconnections; Isolation technology; Random access memory; Space technology; Thermal resistance; Tungsten;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746465
