Title :
Research and design of reconfigurable 64-bit ALU
Author :
Xia, Hong ; Jia, Jingping ; Wei, Shanshan
Author_Institution :
Sch. of Control & Comput. Eng., North China Electr. Power Univ. (NCEPU), Beijing, China
Abstract :
The logic design of ALU, an important constituent part of CPU, is described in this paper. The application of the reconfigurable technology restructures the 8-bit, 16-bit, 32-bit arithmetic and logic operation, performs the arithmetic and logic operation simultaneously, and supports SIMD instructions. This design reduces the size of project effectively, accordingly improves the performance of the ALU. The adder in this design effectively combines the design idea of two-bit-in-one-group and conditional sum, and takes the optimization measures of Manchester carry chain and carry lookahead adder, which makes the basic addition unit increased in speed, reduced in size, and meanwhile lowered in power consumption. The length of the critical path in this design is 13-level logic gates. A simulation of this design has been completed, using the standard SMIC 0.18 μm library, and the anticipative performance index has been achieved.
Keywords :
adders; carry logic; circuit optimisation; logic design; multiprocessing systems; reconfigurable architectures; 13-level logic gate design; CPU; Manchester carry chain optimization; SIMD instruction; arithmetic logic unit; carry lookahead adder; conditional sum; logic design; reconfigurable ALU design; single instruction multiple data; size 0.18 mum; two-bit-in-one-group design; word length 64 bit; Adders; CMOS integrated circuits; CMOS technology; Computer architecture; Computers; Hardware design languages; Logic gates; Manchester carry chain; carry lookahead; conditional carry adder; reconfigurable technology;
Conference_Titel :
Computer Science and Service System (CSSS), 2011 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-9762-1
DOI :
10.1109/CSSS.2011.5972191
