Author :
Asano, I. ; Kunitomo, M. ; Yamamoto, S. ; Furukawa, R. ; Sugawara, Y. ; Uemura, T. ; Kuroda, J. ; Kanai, M. ; Nakata, M. ; Tamaru, T. ; Nakamura, Y. ; Kawagoe, T. ; Yamada, S. ; Kawakita, K. ; Kawamura, H. ; Nakamura, M. ; Morino, M. ; Kisu, T. ; Iijima,
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 1.5 nm equivalent thickness Ta/sub 2/O/sub 5//rugged Si capacitor is demonstrated for mass production of high density DRAMs (Dynamic Random Access Memories). More than 10 years breakdown lifetime of CVD-TiN/Ta/sub 2/O/sub 5//rugged Si capacitor is experimentally clarified for the first time. An excellent pause refresh property is confirmed by using 0.40 mm/sup 2/ DRAM cell as well. This system is applicable to a 0.16 mm/sup 2/ cell for production.
Keywords :
DRAM chips; MOS capacitors; MOS memory circuits; dielectric thin films; integrated circuit manufacture; integrated circuit reliability; leakage currents; semiconductor device breakdown; silicon; tantalum compounds; 1.5 nm; 10 y; 256 Mbit; CVD-TiN/Ta/sub 2/O/sub 5//rugged Si capacitor; DRAM mass production; TDDB characteristic; Ta/sub 2/O/sub 5/ high-k dielectric; TiN-Ta/sub 2/O/sub 5/-Si; breakdown lifetime; dynamic RAM; dynamic random access memories; high density DRAMs; pause refresh property; rugged Si capacitor; Breakdown voltage; Capacitance-voltage characteristics; Capacitors; Electric breakdown; Electric variables; Electric variables measurement; High-K gate dielectrics; Leakage current; Temperature dependence;
